1. Technical Field
The present invention relates generally to an improved memory system, and in particular to a first-in-first-out (FIFO) memory system. Still more particularly, the present invention relates to an improved fall-through FIFO.
2. Description of the Related Art
A FIFO is essentially a data buffer in which data is shifted out in the same chronological order as it was shifted in with the shifting in and shifting out operations typically being asynchronous, thereby enabling the transfer of data between two asynchronous devices. One type of FIFO is a fall-through FIFO. Memory locations in a fall-through FIFO are sequentially associated with each other. In the operation of a fall-through FIFO, the first word to be stored is entered into the first memory location and then automatically ripples down to the last empty memory location in the fall-through FIFO. This empty memory location is the last memory location in an initially empty fall-through FIFO. A second word stored enters into the first location and then ripples down until it comes to the last empty location and then stops, thereby being stored in the second from the last location in the bank of memory locations.
When a word is read out of the memory in the fall-through FIFO, it is read out from the bottom of the memory bank, which would be the first word written into the fall-through FIFO. The second word would then move into the now empty last memory location in the fall-through FIFO.
If, in the mean time, additional words have been written into the fall-through FIFO, these words would have rippled into the locations starting from the second memory location from the bottom of the last location in the fall-through FIFO. Thus, when the first word written is read out of the last location thereof, there would be a rippling effect running up the fall-through FIFO from the last memory location caused by the moving down of each word in succession into the next lower word location of the fall-through FIFO.
With the performance requirements of bus systems, such as a peripheral component interconnection (PCI) bus, burst sizes are increased such that larger fall-through FIFOs are required. For example, presently existing fall-through FIFOs are about 96 bytes in size and designed as a standard fall-through FIFO. By increasing the size of this type of FIFO to 512 bytes for burst sizes of 128 D-words on a PCI bus, the fall-through time is increased. In fact, the fall through time becomes excessive and does not meet the requirements for fall-through FIFOs used for direct memory access.
Therefore, it would be advantageous to have an improved method and apparatus directed towards a FIFO memory system in which the data latency or time needed for data to fall-through the FIFO are minimized.